cmldm7002a cmldm7002ag* CMLDM7002AJ surface mount dual n-channel enhancement-mode silicon mosfet description: these central semiconductor devices are dual enhancement-mode n-channel field effect transistors, manufactured by the n-channel dmos process, designed for high speed pulsed amplifier and driver applications. the cmldm7002a utilizes the usa pinout configuration, while the CMLDM7002AJ utilizes the japanese pinout configuration. these devices offer low r ds (on) and low v ds(on) . marking codes: cmldm7002a: l02 cmldm7002ag*: c2g CMLDM7002AJ: 02j maximum ratings: (t a =25c) symbol units drain-source voltage v ds 60 v drain-gate voltage v dg 60 v gate-source voltage v gs 40 v continuous drain current i d 280 ma continuous source current (body diode) i s 280 ma maximum pulsed drain current i dm 1.5 a maximum pulsed source current i sm 1.5 a power dissipation (note 1) p d 350 mw power dissipation (note 2) p d 300 mw power dissipation (note 3) p d 150 mw operating and storage junction temperature t j , t stg -65 to +150 c thermal resistance ja 357 c/w electrical characteristics per transistor: (t a =25c unless otherwise noted) symbol test conditions min max units i gssf , i gssr v gs =20v, v ds =0 100 na i dss v ds =60v, v gs =0 1.0 a i dss v ds =60v, v gs =0, t j =125c 500 a i d(on) v gs =10v, v ds =10v 500 ma bv dss v gs =0, i d =10a 60 v v gs(th) v ds =v gs , i d =250a 1.0 2.5 v v ds(on) v gs =10v, i d =500ma 1.0 v v ds(on) v gs =5.0v, i d =50ma 0.15 v v sd v gs =0, i s =400ma 1.2 v r ds(on) v gs =10v, i d =500ma 2.0 r ds(on) v gs =10v, i d =500ma, t j =125c 3.5 r ds(on) v gs =5.0v, i d =50ma 3.0 r ds(on) v gs =5.0v, i d =50ma, t j =125c 5.0 g fs v ds =10v, i d =200ma 80 ms notes: (1) ceramic or aluminum core pc board with copper mounting pad area of 4.0mm 2 (2) fr-4 epoxy pc board with copper mounting pad area of 4.0mm 2 (3) fr-4 epoxy pc board with copper mounting pad area of 1.4mm 2 * device is halogen free by design sot-563 case r5 (18-january 2010) www.centralsemi.com
cmldm7002a cmldm7002ag* CMLDM7002AJ surface mount dual n-channel enhancement-mode silicon mosfet sot-563 case - mechanical outline lead code: 1) gate q1 2) source q1 3) drain q2 4) gate q2 5) source q2 6) drain q1 marking codes: cmldm7002a: l02 cmldm7002ag*: c2g pin configurations electrical characteristics per transistor - continued: (t a =25c unless otherwise noted) symbol test conditions min max units c rss v ds =25v, v gs =0, f=1.0mhz 5.0 pf c iss v ds =25v, v gs =0, f=1.0mhz 50 pf c oss v ds =25v, v gs =0, f=1.0mhz 25 pf t on / t off v dd =30v, v gs =10v, i d =200ma r g =25, r l =150 20 ns cmldm7002a (usa pinout) cmldm7002ag* lead code: 1) source q1 2) gate q1 3) drain q2 4) source q2 5) gate q2 6) drain q1 marking code: 02j CMLDM7002AJ (japanese pinout) * device is halogen free by design www.centralsemi.com r5 (18-january 2010)
|
